In interface standards, such as representatively Serial ATA, a clock signal having a high frequency of 1.5 GHz is required, which is typically generated from a reference clock signal having a low frequency of about 25 MHz by means of the multiplication function of a PLL. For example, by using a PLL capable of 60-fold multiplication, a reference clock signal of 25 MHz can be used to generate a clock signal of 1.5 GHz (=25 MHz*60). Further, if a fractional-N frequency division circuit technique using ΔΣ modulation is employed, the 1.5-GHz clock signal can be generated from an output frequency of 16.934 MHz or 27 MHz of a quartz oscillator.
In conventional typical PLLs, the output voltage of a loop filter is in the vicinity of zero during its start-up, and therefore, the gate-source voltage of an NMOS transistor included in a voltage-current converting circuit does not exceed the threshold, so that the output current of the voltage-current converting circuit becomes substantially zero. As a result, the frequency of an output clock signal becomes 0 Hz, and the output of the PLL has a high impedance. If no disturbance or the like occurs, the PLL is normally started up by a feedback action. However, if incoming high-frequency noise is frequency-divided by a divider, then when the resultant frequency is higher than a reference clock signal, the PLL performs an operation so as to lower the frequency of the output clock signal. As a result, the output voltage of the loop filter remains zero, so that the PLL fails to be started up.
To solve the problem above, a conventional technique has been proposed in which two PLLs having different capture ranges and jitters are provided and switched between during start-up and during a normal operation (see, for example, Patent Document 1). Another technique has been proposed in which a PLL is more quickly returned to a normal operation mode from a standby mode, and a start-up circuit is provided in the PLL (see, for example, Patent Document 2).
Patent Document 1: Japanese Unexamined Patent Application Publication No. H10-290161
Patent Document 2: U.S. Pat. No. 6,407,600